#ifndef __SN32F290_CT16_H
#define __SN32F290_CT16_H

/*_____ I N C L U D E S ____________________________________________________*/

/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4000 0000 (CT16B0)
							0x4000 2000 (CT16B1)
							0x4000 4000 (CT16B2)
							0x4000 6000 (CT16B3)
							0x4000 8000 (CT16B4)
							0x4000 A000 (CT16B5)
*/

/* CT16Bn Timer Control register <CT16Bn_TMRCTRL> (0x00) */
																					//[0:0] Counter enable bit
#define	CT16_CEN_DIS 								0			//Enable
#define	CT16_CEN_EN  								1			//Disable
#define mskCT16_CEN_DIS							(CT16_CEN_DIS << 0)
#define	mskCT16_CEN_EN  						(CT16_CEN_EN << 0)

																					//[1:1] Counter reset bit
#define	CT16_CRST 									1			
#define mskCT16_CRST								(CT16_CRST << 1)	

																					//[2:2] PCLK source
#define CT16_CLKSEL_HCLK						0
#define CT16_CLKSEL_PLL_VCO					1
#define CT16_CLKSEL_ILRC						2
#define mskCT16_CLKSEL_HCLK					(CT16_CLKSEL_HCLK << 2)
#define mskCT16_CLKSEL_PLL_VCO			(CT16_CLKSEL_PLL_VCO << 2)
#define mskCT16_CLKSEL_ILRC					(CT16_CLKSEL_ILRC << 2)

																					//[6:4] Counting mode selection 
#define CT16_CM_EDGE_UP							0			//Edge-aligned Up-counting mode
#define CT16_CM_EDGE_DOWN						1			//Edge-aligned Down-counting mode
#define CT16_CM_CENTER_DOWN					2			//Center-aligned mode 1. Match interrupt is set during down-counting period
#define CT16_CM_CENTER_UP						4			//Center-aligned mode 2. Match interrupt is set during up-counting period
#define CT16_CM_CENTER_BOTH					6			//Center-aligned mode 3. Match interrupt is set during both up and down period.
#define mskCT16_CM_EDGE_UP					(CT16_CM_EDGE_UP << 4)		
#define mskCT16_CM_EDGE_DOWN				(CT16_CM_EDGE_DOWN << 4)
#define mskCT16_CM_CENTER_DOWN			(CT16_CM_CENTER_DOWN << 4)
#define mskCT16_CM_CENTER_UP				(CT16_CM_CENTER_UP << 4)	
#define mskCT16_CM_CENTER_BOTH			(CT16_CM_CENTER_BOTH << 4)

/* CT16Bn Count Control register <CT16Bn_CNTCTRL> (0x10) */
																					//[1:0] Count/Timer Mode selection.
#define	CT16_CTM_TIMER							0			//Timer mode: Every rising PCLK edge.
#define CT16_CTM_CNTER_RISING				1			//Counter mode: TC increments on rising edge of CAP input.
#define CT16_CTM_CNTER_FALLING			2			//Counter mode: TC increments on falling edge of CAP input.
#define CT16_CTM_CNTER_BOTH					3			//Counter mode: TC increments on both edge of CAP input.
#define	mskCT16_CTM_TIMER						(CT16_CTM_TIMER << 0)		
#define mskCT16_CTM_CNTER_RISING		(CT16_CTM_CNTER_RISING << 0)		
#define mskCT16_CTM_CNTER_FALLING		(CT16_CTM_CNTER_FALLING << 0)		
#define mskCT16_CTM_CNTER_BOTH			(CT16_CTM_CNTER_BOTH << 0)		

/* CT16Bn Match Control register <CT16Bn_MCTRL> (0x14) */
#define	CT16_MRnIE_EN								1		
#define	CT16_MRnIE_DIS							0
#define	CT16_MRnRST_EN							1		
#define	CT16_MRnRST_DIS							0
#define	CT16_MRnSTOP_EN							1		
#define	CT16_MRnSTOP_DIS						0

																					//[0:0] Enable MR0 match interrupt
#define mskCT16_MR0IE_EN						(CT16_MRnIE_EN << 0)
#define mskCT16_MR0IE_DIS						(CT16_MRnIE_DIS << 0)

																					//[1:1] Enable reset TC when MR0 matches TC.
#define mskCT16_MR0RST_EN						(CT16_MRnRST_EN << 1)
#define mskCT16_MR0RST_DIS					(CT16_MRnRST_DIS << 1)

																					//[2:2] Enable stop TC and clear CEN when MR0 matches TC.
#define mskCT16_MR0STOP_EN					(CT16_MRnSTOP_EN << 2)
#define mskCT16_MR0STOP_DIS					(CT16_MRnSTOP_DIS << 2)

																					//[3:3] Enable MR1 match interrupt
#define mskCT16_MR1IE_EN						(CT16_MRnIE_EN << 3)
#define mskCT16_MR1IE_DIS						(CT16_MRnIE_DIS << 3)

																					//[4:4] Enable reset TC when MR1 matches TC.
#define mskCT16_MR1RST_EN						(CT16_MRnRST_EN << 4)
#define mskCT16_MR1RST_DIS					(CT16_MRnRST_DIS << 4)

																					//[5:5] Enable stop TC and clear CEN when MR1 matches TC.	
#define mskCT16_MR1STOP_EN					(CT16_MRnSTOP_EN << 5)
#define mskCT16_MR1STOP_DIS					(CT16_MRnSTOP_DIS << 5)

																					//[6:6] Enable MR2 match interrupt
#define mskCT16_MR2IE_EN						(CT16_MRnIE_EN << 6)
#define mskCT16_MR2IE_DIS						(CT16_MRnIE_DIS << 6)

																					//[7:7] Enable reset TC when MR2 matches TC.
#define mskCT16_MR2RST_EN						(CT16_MRnRST_EN << 7)
#define mskCT16_MR2RST_DIS					(CT16_MRnRST_DIS << 7)

																					//[8:8] Enable stop TC and clear CEN when MR2 matches TC.
#define mskCT16_MR2STOP_EN					(CT16_MRnSTOP_EN << 8)
#define mskCT16_MR2STOP_DIS					(CT16_MRnSTOP_DIS << 8)

																					//[9:9] Enable MR3 match interrupt
#define mskCT16_MR3IE_EN						(CT16_MRnIE_EN << 9)
#define mskCT16_MR3IE_DIS						(CT16_MRnIE_DIS << 9)

																					//[10:10] Enable reset TC when MR3 matches TC.		
#define mskCT16_MR3RST_EN						(CT16_MRnRST_EN << 10)
#define mskCT16_MR3RST_DIS					(CT16_MRnRST_DIS << 10)

																					//[11:11] Enable stop TC and clear CEN when MR3 matches TC.
#define mskCT16_MR3STOP_EN					(CT16_MRnSTOP_EN << 11)
#define mskCT16_MR3STOP_DIS					(CT16_MRnSTOP_DIS << 11)

																					//[21:21] Enable MR9 match interrupt
#define mskCT16_MR9IE_EN						(CT16_MRnIE_EN << 21)
#define mskCT16_MR9IE_DIS						(CT16_MRnIE_DIS << 21)

																					//[22:22] Enable reset TC when MR9 matches TC.
#define mskCT16_MR9RST_EN						(CT16_MRnRST_EN << 22)
#define mskCT16_MR9RST_DIS					(CT16_MRnRST_DIS << 22)

																					//[23:23] Enable stop TC and clear CEN when MR9 matches TC.
#define mskCT16_MR9STOP_EN					(CT16_MRnSTOP_EN << 23)
#define mskCT16_MR9STOP_DIS					(CT16_MRnSTOP_DIS << 23)

/* CT16Bn Match Control register <CT16Bn_MCTRL> (0x14) (CT16B1 only) */
																					//[0:0] Enable MR0 match interrupt
#define mskCT16B1_MR0IE_EN					(CT16_MRnIE_EN << 0)
#define mskCT16B1_MR0IE_DIS					(CT16_MRnIE_DIS << 0)

																					//[1:1] Enable reset TC when MR0 matches TC.
#define mskCT16B1_MR0RST_EN					(CT16_MRnRST_EN << 1)
#define mskCT16B1_MR0RST_DIS				(CT16_MRnRST_DIS << 1)

																					//[2:2] Enable stop TC and clear CEN when MR0 matches TC.
#define mskCT16B1_MR0STOP_EN				(CT16_MRnSTOP_EN << 2)
#define mskCT16B1_MR0STOP_DIS				(CT16_MRnSTOP_DIS << 2)

																					//[3:3] Enable MR1 match interrupt
#define mskCT16B1_MR1IE_EN					(CT16_MRnIE_EN << 3)
#define mskCT16B1_MR1IE_DIS					(CT16_MRnIE_DIS << 3)

																					//[4:4] Enable reset TC when MR1 matches TC.
#define mskCT16B1_MR1RST_EN					(CT16_MRnRST_EN << 4)
#define mskCT16B1_MR1RST_DIS				(CT16_MRnRST_DIS << 4)

																					//[5:5] Enable stop TC and clear CEN when MR1 matches TC.	
#define mskCT16B1_MR1STOP_EN				(CT16_MRnSTOP_EN << 5)
#define mskCT16B1_MR1STOP_DIS				(CT16_MRnSTOP_DIS << 5)

																					//[6:6] Enable MR2 match interrupt
#define mskCT16B1_MR2IE_EN					(CT16_MRnIE_EN << 6)
#define mskCT16B1_MR2IE_DIS					(CT16_MRnIE_DIS << 6)

																					//[7:7] Enable reset TC when MR2 matches TC.
#define mskCT16B1_MR2RST_EN					(CT16_MRnRST_EN << 7)
#define mskCT16B1_MR2RST_DIS				(CT16_MRnRST_DIS << 7)

																					//[8:8] Enable stop TC and clear CEN when MR2 matches TC.
#define mskCT16B1_MR2STOP_EN				(CT16_MRnSTOP_EN << 8)
#define mskCT16B1_MR2STOP_DIS				(CT16_MRnSTOP_DIS << 8)

																					//[9:9] Enable MR3 match interrupt
#define mskCT16B1_MR3IE_EN					(CT16_MRnIE_EN << 9)
#define mskCT16B1_MR3IE_DIS					(CT16_MRnIE_DIS << 9)

																					//[10:10] Enable reset TC when MR3 matches TC.		
#define mskCT16B1_MR3RST_EN					(CT16_MRnRST_EN << 10)
#define mskCT16B1_MR3RST_DIS				(CT16_MRnRST_DIS << 10)

																					//[11:11] Enable stop TC and clear CEN when MR3 matches TC.
#define mskCT16B1_MR3STOP_EN				(CT16_MRnSTOP_EN << 11)
#define mskCT16B1_MR3STOP_DIS				(CT16_MRnSTOP_DIS << 11)

																					//[12:12] Enable MR4 match interrupt
#define mskCT16B1_MR4IE_EN					(CT16_MRnIE_EN << 12)
#define mskCT16B1_MR4IE_DIS					(CT16_MRnIE_DIS << 12)

																					//[13:13] Enable reset TC when MR4 matches TC.	
#define mskCT16B1_MR4RST_EN					(CT16_MRnRST_EN << 13)
#define mskCT16B1_MR4RST_DIS				(CT16_MRnRST_DIS << 13)

																					//[14:14] Enable stop TC and clear CEN when MR4 matches TC.
#define mskCT16B1_MR4STOP_EN				(CT16_MRnSTOP_EN << 14)
#define mskCT16B1_MR4STOP_DIS				(CT16_MRnSTOP_DIS << 14)

																					//[15:15] Enable MR5 match interrupt
#define mskCT16B1_MR5IE_EN					(CT16_MRnIE_EN << 15)
#define mskCT16B1_MR5IE_DIS					(CT16_MRnIE_DIS << 15)

																					//[16:16] Enable reset TC when MR5 matches TC.	
#define mskCT16B1_MR5RST_EN					(CT16_MRnRST_EN << 16)
#define mskCT16B1_MR5RST_DIS				(CT16_MRnRST_DIS << 16)

																					//[17:17] Enable stop TC and clear CEN when MR5 matches TC.
#define mskCT16B1_MR5STOP_EN				(CT16_MRnSTOP_EN << 17)
#define mskCT16B1_MR5STOP_DIS				(CT16_MRnSTOP_DIS << 17)

																					//[18:18] Enable MR6 match interrupt
#define mskCT16B1_MR6IE_EN					(CT16_MRnIE_EN << 18)
#define mskCT16B1_MR6IE_DIS					(CT16_MRnIE_DIS << 18)

																					//[19:19] Enable reset TC when MR6 matches TC.	
#define mskCT16B1_MR6RST_EN					(CT16_MRnRST_EN << 19)
#define mskCT16B1_MR6RST_DIS				(CT16_MRnRST_DIS << 19)

																					//[20:20] Enable stop TC and clear CEN when MR6 matches TC.
#define mskCT16B1_MR6STOP_EN				(CT16_MRnSTOP_EN << 20)
#define mskCT16B1_MR6STOP_DIS				(CT16_MRnSTOP_DIS << 20)

																					//[21:21] Enable MR7 match interrupt
#define mskCT16B1_MR7IE_EN					(CT16_MRnIE_EN << 21)
#define mskCT16B1_MR7IE_DIS					(CT16_MRnIE_DIS << 21)

																					//[22:22] Enable reset TC when MR7 matches TC.
#define mskCT16B1_MR7RST_EN					(CT16_MRnRST_EN << 22)
#define mskCT16B1_MR7RST_DIS				(CT16_MRnRST_DIS << 22)

																					//[23:23] Enable stop TC and clear CEN when MR7 matches TC.
#define mskCT16B1_MR7STOP_EN				(CT16_MRnSTOP_EN << 23)
#define mskCT16B1_MR7STOP_DIS				(CT16_MRnSTOP_DIS << 23)

																					//[24:24] Enable MR8 match interrupt
#define mskCT16B1_MR8IE_EN					(CT16_MRnIE_EN << 24)
#define mskCT16B1_MR8IE_DIS					(CT16_MRnIE_DIS << 24)

																					//[25:25] Enable reset TC when MR8 matches TC.	
#define mskCT16B1_MR8RST_EN					(CT16_MRnRST_EN << 25)
#define mskCT16B1_MR8RST_DIS				(CT16_MRnRST_DIS << 25)

																					//[26:26] Enable stop TC and clear CEN when MR8 matches TC.
#define mskCT16B1_MR8STOP_EN				(CT16_MRnSTOP_EN << 26)
#define mskCT16B1_MR8STOP_DIS				(CT16_MRnSTOP_DIS << 26)

																					//[27:27] Enable MR9 match interrupt
#define mskCT16B1_MR9IE_EN					(CT16_MRnIE_EN << 27)
#define mskCT16B1_MR9IE_DIS					(CT16_MRnIE_DIS << 27)

																					//[28:28] Enable reset TC when MR9 matches TC.
#define mskCT16B1_MR9RST_EN					(CT16_MRnRST_EN << 28)
#define mskCT16B1_MR9RST_DIS				(CT16_MRnRST_DIS << 28)

																					//[29:29] Enable stop TC and clear CEN when MR9 matches TC.
#define mskCT16B1_MR9STOP_EN				(CT16_MRnSTOP_EN << 29)
#define mskCT16B1_MR9STOP_DIS				(CT16_MRnSTOP_DIS << 29)

/* CT16Bn Match Control register2 <CT16Bn_MCTRL> (0x18) (CT16B1 only) */
																					//[0:0] Enable MR10 match interrupt
#define mskCT16B1_MR10IE_EN					(CT16_MRnIE_EN << 0)
#define mskCT16B1_MR10IE_DIS				(CT16_MRnIE_DIS << 0)

																					//[1:1] Enable reset TC when MR10 matches TC.
#define mskCT16B1_MR10RST_EN				(CT16_MRnRST_EN << 1)
#define mskCT16B1_MR10RST_DIS				(CT16_MRnRST_DIS << 1)

																					//[2:2] Enable stop TC and clear CEN when MR10 matches TC.
#define mskCT16B1_MR10STOP_EN				(CT16_MRnSTOP_EN << 2)
#define mskCT16B1_MR10STOP_DIS			(CT16_MRnSTOP_DIS << 2)

																					//[3:3] Enable MR11 match interrupt
#define mskCT16B1_MR11IE_EN					(CT16_MRnIE_EN << 3)
#define mskCT16B1_MR11IE_DIS				(CT16_MRnIE_DIS << 3)

																					//[4:4] Enable reset TC when MR11 matches TC.
#define mskCT16B1_MR11RST_EN				(CT16_MRnRST_EN << 4)
#define mskCT16B1_MR11RST_DIS				(CT16_MRnRST_DIS << 4)

																					//[5:5] Enable stop TC and clear CEN when MR11 matches TC.
#define mskCT16B1_MR11STOP_EN				(CT16_MRnSTOP_EN << 5)
#define mskCT16B1_MR11STOP_DIS			(CT16_MRnSTOP_DIS << 5)

																					//[6:6] Enable MR12 match interrupt
#define mskCT16B1_MR12IE_EN					(CT16_MRnIE_EN << 6)
#define mskCT16B1_MR12IE_DIS				(CT16_MRnIE_DIS << 6)

																					//[7:7] Enable reset TC when MR12 matches TC.
#define mskCT16B1_MR12RST_EN				(CT16_MRnRST_EN << 7)
#define mskCT16B1_MR12RST_DIS				(CT16_MRnRST_DIS << 7)

																					//[8:8] Enable stop TC and clear CEN when MR12 matches TC.
#define mskCT16B1_MR12STOP_EN				(CT16_MRnSTOP_EN << 8)
#define mskCT16B1_MR12STOP_DIS			(CT16_MRnSTOP_DIS << 8)

/* CT16Bn Capture Control register <CT16Bn_CAPCTRL> (0x84) */
																					//[0:0] Enable CAP0 capture on rising edge.
#define	CT16_CAP0RE_EN							1		
#define	CT16_CAP0RE_DIS							0
#define mskCT16_CAP0RE_EN						(CT16_CAP0RE_EN << 0)
#define mskCT16_CAP0RE_DIS					(CT16_CAP0RE_DIS << 0)

																					//[1:1] Enable CAP0 capture on fallng edge.
#define	CT16_CAP0FE_EN							1		
#define	CT16_CAP0FE_DIS							0
#define mskCT16_CAP0FE_EN						(CT16_CAP0FE_EN << 1)
#define mskCT16_CAP0FE_DIS					(CT16_CAP0FE_DIS << 1)

																					//[2:2] Enable CAP0 interrupt.
#define	CT16_CAP0IE_EN							1		
#define	CT16_CAP0IE_DIS							0
#define mskCT16_CAP0IE_EN						(CT16_CAP0IE_EN << 2)
#define mskCT16_CAP0IE_DIS					(CT16_CAP0IE_DIS << 2)

																					//[3:3] Enable CAP0 function.
#define	CT16_CAP0EN_EN							1		
#define	CT16_CAP0EN_DIS							0
#define mskCT16_CAP0EN_EN						(CT16_CAP0EN_EN << 3)
#define mskCT16_CAP0EN_DIS					(CT16_CAP0EN_DIS << 3)

/* CT16Bn External Match register <CT16Bn_EM> (0x8C) */
																					//[0:0] CT16Bn PWM0 drive state
#define	CT16_EM0										1		
#define mskCT16_EM0									(CT16_EM0 << 0)
																					//[1:1] CT16Bn PWM1 drive state
#define	CT16_EM1										1		
#define mskCT16_EM1									(CT16_EM1 << 1)
																					//[2:2] CT16Bn PWM2 drive state
#define	CT16_EM2										1		
#define mskCT16_EM2									(CT16_EM2 << 2)
																					//[3:3] CT16Bn PWM3 drive state
#define	CT16_EM3										1			
#define mskCT16_EM3									(CT16_EM3 << 3)
																					//[4:4] CT16Bn PWM4 drive state
#define	CT16_EM4										1		
#define mskCT16_EM4									(CT16_EM4 << 4)
																					//[5:5] CT16Bn PWM5 drive state
#define	CT16_EM5										1		
#define mskCT16_EM5									(CT16_EM5 << 5)
																					//[6:6] CT16Bn PWM6 drive state
#define	CT16_EM6										1		
#define mskCT16_EM6									(CT16_EM6 << 6)
																					//[7:7] CT16Bn PWM7 drive state
#define	CT16_EM7										1		
#define mskCT16_EM7									(CT16_EM7 << 7)
																					//[8:8] CT16Bn PWM8 drive state
#define	CT16_EM8										1		
#define mskCT16_EM8									(CT16_EM8 << 8)
																					//[9:9] CT16Bn PWM9 drive state
#define	CT16_EM9										1		
#define mskCT16_EM9									(CT16_EM9 << 9)
																					//[10:10] CT16Bn PWM10 drive state
#define	CT16_EM10										1		
#define mskCT16_EM10								(CT16_EM10 << 10)
																					//[11:11] CT16Bn PWM11 drive state
#define	CT16_EM11										1		
#define mskCT16_EM11								(CT16_EM11 << 11)

																		
#define	CT16_EMC_DO_NOTHING					0			//Do nothing.
#define	CT16_EMC_LOW								1			//CT16Bn PWMn pin is low.
#define	CT16_EMC_HIGH								2			//CT16Bn PWMn pin is high.
#define	CT16_EMC_TOGGLE							3			//Toggle CT16Bn PWMn pin.

																					//[5:4] CT16Bn PWM0 functionality
#define mskCT16_EMC0_DO_NOTHING			(CT16_EMC_LOW << 4)
#define mskCT16_EMC0_LOW						(CT16_EMC_LOW << 4)
#define mskCT16_EMC0_HIGH						(CT16_EMC_HIGH << 4)
#define mskCT16_EMC0_TOGGLE					(CT16_EMC_TOGGLE << 4)

																					//[7:6] CT16Bn PWM1 functionality
#define mskCT16_EMC1_DO_NOTHING			(CT16_EMC_LOW << 6)
#define mskCT16_EMC1_LOW						(CT16_EMC_LOW << 6)
#define mskCT16_EMC1_HIGH						(CT16_EMC_HIGH << 6)
#define mskCT16_EMC1_TOGGLE					(CT16_EMC_TOGGLE << 6)

																					//[9:8] CT16Bn PWM2 functionality
#define mskCT16_EMC2_DO_NOTHING			(CT16_EMC_LOW << 8)
#define mskCT16_EMC2_LOW						(CT16_EMC_LOW << 8)
#define mskCT16_EMC2_HIGH						(CT16_EMC_HIGH << 8)
#define mskCT16_EMC2_TOGGLE					(CT16_EMC_TOGGLE << 8)

																					//[11:10] CT16Bn PWM3 functionality
#define mskCT16_EMC3_DO_NOTHING			(CT16_EMC_LOW << 10)
#define mskCT16_EMC3_LOW						(CT16_EMC_LOW << 10)
#define mskCT16_EMC3_HIGH						(CT16_EMC_HIGH << 10)
#define mskCT16_EMC3_TOGGLE					(CT16_EMC_TOGGLE << 10)

/* CT16Bn External Match Control register <CT16Bn_EMC> (0x90) (CT16B1 only) */
																					//[1:0] CT16Bn PWM0 functionality
#define mskCT16B1_EMC0_DO_NOTHING		(CT16_EMC_LOW << 0)
#define mskCT16B1_EMC0_LOW					(CT16_EMC_LOW << 0)
#define mskCT16B1_EMC0_HIGH					(CT16_EMC_HIGH << 0)
#define mskCT16B1_EMC0_TOGGLE				(CT16_EMC_TOGGLE << 0)

																					//[3:2] CT16Bn PWM1 functionality
#define mskCT16B1_EMC1_DO_NOTHING		(CT16_EMC_LOW << 2)
#define mskCT16B1_EMC1_LOW					(CT16_EMC_LOW << 2)
#define mskCT16B1_EMC1_HIGH					(CT16_EMC_HIGH << 2)
#define mskCT16B1_EMC1_TOGGLE				(CT16_EMC_TOGGLE << 2)

																					//[5:4] CT16Bn PWM2 functionality
#define mskCT16B1_EMC2_DO_NOTHING		(CT16_EMC_LOW << 4)
#define mskCT16B1_EMC2_LOW					(CT16_EMC_LOW << 4)
#define mskCT16B1_EMC2_HIGH					(CT16_EMC_HIGH << 4)
#define mskCT16B1_EMC2_TOGGLE				(CT16_EMC_TOGGLE << 4)

																					//[7:6] CT16Bn PWM3 functionality
#define mskCT16B1_EMC3_DO_NOTHING		(CT16_EMC_LOW << 6)
#define mskCT16B1_EMC3_LOW					(CT16_EMC_LOW << 6)
#define mskCT16B1_EMC3_HIGH					(CT16_EMC_HIGH << 6)
#define mskCT16B1_EMC3_TOGGLE				(CT16_EMC_TOGGLE << 6)

																					//[9:8] CT16Bn PWM4 functionality
#define mskCT16B1_EMC4_DO_NOTHING		(CT16_EMC_LOW << 8)
#define mskCT16B1_EMC4_LOW					(CT16_EMC_LOW << 8)
#define mskCT16B1_EMC4_HIGH					(CT16_EMC_HIGH << 8)
#define mskCT16B1_EMC4_TOGGLE				(CT16_EMC_TOGGLE << 8)

																					//[11:10] CT16Bn PWM5 functionality
#define mskCT16B1_EMC5_DO_NOTHING		(CT16_EMC_LOW << 10)
#define mskCT16B1_EMC5_LOW					(CT16_EMC_LOW << 10)
#define mskCT16B1_EMC5_HIGH					(CT16_EMC_HIGH << 10)
#define mskCT16B1_EMC5_TOGGLE				(CT16_EMC_TOGGLE << 10)

																					//[13:12] CT16Bn PWM6 functionality
#define mskCT16B1_EMC6_DO_NOTHING		(CT16_EMC_LOW << 12)
#define mskCT16B1_EMC6_LOW					(CT16_EMC_LOW << 12)
#define mskCT16B1_EMC6_HIGH					(CT16_EMC_HIGH << 12)
#define mskCT16B1_EMC6_TOGGLE				(CT16_EMC_TOGGLE << 12)

																					//[15:14] CT16Bn PWM7 functionality
#define mskCT16B1_EMC7_DO_NOTHING		(CT16_EMC_LOW << 14)
#define mskCT16B1_EMC7_LOW					(CT16_EMC_LOW << 14)
#define mskCT16B1_EMC7_HIGH					(CT16_EMC_HIGH << 14)
#define mskCT16B1_EMC7_TOGGLE				(CT16_EMC_TOGGLE << 14)

																					//[17:16] CT16Bn PWM8 functionality
#define mskCT16B1_EMC8_DO_NOTHING		(CT16_EMC_LOW << 16)
#define mskCT16B1_EMC8_LOW					(CT16_EMC_LOW << 16)
#define mskCT16B1_EMC8_HIGH					(CT16_EMC_HIGH << 16)
#define mskCT16B1_EMC8_TOGGLE				(CT16_EMC_TOGGLE << 16)

																					//[19:18] CT16Bn PWM9 functionality
#define mskCT16B1_EMC9_DO_NOTHING		(CT16_EMC_LOW << 18)
#define mskCT16B1_EMC9_LOW					(CT16_EMC_LOW << 18)
#define mskCT16B1_EMC9_HIGH					(CT16_EMC_HIGH << 18)
#define mskCT16B1_EMC9_TOGGLE				(CT16_EMC_TOGGLE << 18)

																					//[21:20] CT16Bn PWM10 functionality
#define mskCT16B1_EMC10_DO_NOTHING	(CT16_EMC_LOW << 20)
#define mskCT16B1_EMC10_LOW					(CT16_EMC_LOW << 20)
#define mskCT16B1_EMC10_HIGH				(CT16_EMC_HIGH << 20)
#define mskCT16B1_EMC10_TOGGLE			(CT16_EMC_TOGGLE << 20)

																					//[23:22] CT16Bn PWM11 functionality
#define mskCT16B1_EMC11_DO_NOTHING	(CT16_EMC_LOW << 22)
#define mskCT16B1_EMC11_LOW					(CT16_EMC_LOW << 22)
#define mskCT16B1_EMC11_HIGH				(CT16_EMC_HIGH << 22)
#define mskCT16B1_EMC11_TOGGLE			(CT16_EMC_TOGGLE << 22)

/* CT16Bn PWM Control register <CT16Bn_PWMCTRL> (0x98) */
#define	CT16_PWMnEN_EN							1	// CT16Bn PWMn is enabled for PWM mode.	
#define	CT16_PWMnEN_EMn							0 // CT16Bn PWMn is controlled by EMn.

																			//[0:0] CT16Bn PWM0 enable.
#define mskCT16_PWM0EN_EN						(CT16_PWMnEN_EN << 0)
#define mskCT16_PWM0EN_EM0					(CT16_PWMnEN_EMn << 0)

																			//[1:1] CT16Bn PWM1 enable.
#define mskCT16_PWM1EN_EN						(CT16_PWMnEN_EN << 1)
#define mskCT16_PWM1EN_EM1					(CT16_PWMnEN_EMn << 1)

																			//[2:2] CT16Bn PWM2 enable.
#define mskCT16_PWM2EN_EN						(CT16_PWMnEN_EN << 2)
#define mskCT16_PWM2EN_EM2					(CT16_PWMnEN_EMn << 2)

																			//[3:3] CT16Bn PWM3 enable.
#define mskCT16_PWM3EN_EN						(CT16_PWMnEN_EN << 3)
#define mskCT16_PWM3EN_EM3					(CT16_PWMnEN_EMn << 3)

#define	CT16_PWMnMODE_1							0	// PWMn mode 1.	
#define	CT16_PWMnMODE_2							1 // PWMn mode 2.
#define	CT16_PWMnMODE_FORCE_0				2 // Force 0.
#define	CT16_PWMnMODE_FORCE_1				3 // Force 1.

																			//[5:4] CT16Bn PWM0 output mode.
#define mskCT16_PWM0MODE_1					(CT16_PWMnMODE_1 << 4)
#define mskCT16_PWM0MODE_2					(CT16_PWMnMODE_2 << 4)
#define mskCT16_PWM0MODE_FORCE_0		(CT16_PWMnMODE_FORCE_0 << 4)
#define mskCT16_PWM0MODE_FORCE_1		(CT16_PWMnMODE_FORCE_1 << 4)

																			//[7:6] CT16Bn PWM1 output mode.
#define mskCT16_PWM1MODE_1					(CT16_PWMnMODE_1 << 6)
#define mskCT16_PWM1MODE_2					(CT16_PWMnMODE_2 << 6)
#define mskCT16_PWM1MODE_FORCE_0		(CT16_PWMnMODE_FORCE_0 << 6)
#define mskCT16_PWM1MODE_FORCE_1		(CT16_PWMnMODE_FORCE_1 << 6)

																			//[9:8] CT16Bn PWM2 output mode.
#define mskCT16_PWM2MODE_1					(CT16_PWMnMODE_1 << 8)
#define mskCT16_PWM2MODE_2					(CT16_PWMnMODE_2 << 8)
#define mskCT16_PWM2MODE_FORCE_0		(CT16_PWMnMODE_FORCE_0 << 8)
#define mskCT16_PWM2MODE_FORCE_1		(CT16_PWMnMODE_FORCE_1 << 8)

																			//[11:10] CT16Bn PWM3 output mode.
#define mskCT16_PWM3MODE_1					(CT16_PWMnMODE_1 << 10)
#define mskCT16_PWM3MODE_2					(CT16_PWMnMODE_2 << 10)
#define mskCT16_PWM3MODE_FORCE_0		(CT16_PWMnMODE_FORCE_0 << 10)
#define mskCT16_PWM3MODE_FORCE_1		(CT16_PWMnMODE_FORCE_1 << 10)

#define	CT16_PWMnIOEN_EN						1	// PWMn pin acts as match output.
#define	CT16_PWMnIOEN_DIS						0	// PWMn pin acts as GPIO.	

																			//[20:20] CT16Bn PWM0 IO selection.
#define mskCT16_PWM0IOEN_EN					(CT16_PWMnIOEN_EN << 20)
#define mskCT16_PWM0IOEN_DIS				(CT16_PWMnIOEN_DIS << 20)

																			//[21:21] CT16Bn PWM1 IO selection.
#define mskCT16_PWM1IOEN_EN					(CT16_PWMnIOEN_EN << 21)
#define mskCT16_PWM1IOEN_DIS				(CT16_PWMnIOEN_DIS << 21)

																			//[22:22] CT16Bn PWM2 IO selection.
#define mskCT16_PWM2IOEN_EN					(CT16_PWMnIOEN_EN << 22)
#define mskCT16_PWM2IOEN_DIS				(CT16_PWMnIOEN_DIS << 22)

																			//[23:23] CT16Bn PWM3 IO selection.
#define mskCT16_PWM3IOEN_EN					(CT16_PWMnIOEN_EN << 23)
#define mskCT16_PWM3IOEN_DIS				(CT16_PWMnIOEN_DIS << 23)

/* CT16Bn PWM Control register <CT16Bn_PWMCTRL> (0x98) (CT16B1 only)*/
																			//[1:0] CT16Bn PWM0 output mode.
#define mskCT16B1_PWM0MODE_1				(CT16_PWMnMODE_1 << 0)
#define mskCT16B1_PWM0MODE_2				(CT16_PWMnMODE_2 << 0)
#define mskCT16B1_PWM0MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 0)
#define mskCT16B1_PWM0MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 0)

																			//[3:2] CT16Bn PWM1 output mode.
#define mskCT16B1_PWM1MODE_1				(CT16_PWMnMODE_1 << 2)
#define mskCT16B1_PWM1MODE_2				(CT16_PWMnMODE_2 << 2)
#define mskCT16B1_PWM1MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 2)
#define mskCT16B1_PWM1MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 2)

																			//[5:4] CT16Bn PWM2 output mode.
#define mskCT16B1_PWM2MODE_1				(CT16_PWMnMODE_1 << 4)
#define mskCT16B1_PWM2MODE_2				(CT16_PWMnMODE_2 << 4)
#define mskCT16B1_PWM2MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 4)
#define mskCT16B1_PWM2MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 4)

																			//[7:6] CT16Bn PWM3 output mode.
#define mskCT16B1_PWM3MODE_1				(CT16_PWMnMODE_1 << 6)
#define mskCT16B1_PWM3MODE_2				(CT16_PWMnMODE_2 << 6)
#define mskCT16B1_PWM3MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 6)
#define mskCT16B1_PWM3MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 6)

																			//[9:8] CT16Bn PWM4 output mode.
#define mskCT16B1_PWM4MODE_1				(CT16_PWMnMODE_1 << 8)
#define mskCT16B1_PWM4MODE_2				(CT16_PWMnMODE_2 << 8)
#define mskCT16B1_PWM4MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 8)
#define mskCT16B1_PWM4MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 8)

																			//[11:10] CT16Bn PWM5 output mode.
#define mskCT16B1_PWM5MODE_1				(CT16_PWMnMODE_1 << 10)
#define mskCT16B1_PWM5MODE_2				(CT16_PWMnMODE_2 << 10)
#define mskCT16B1_PWM5MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 10)
#define mskCT16B1_PWM5MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 10)

																			//[13:12] CT16Bn PWM6 output mode.
#define mskCT16B1_PWM6MODE_1				(CT16_PWMnMODE_1 << 12)
#define mskCT16B1_PWM6MODE_2				(CT16_PWMnMODE_2 << 12)
#define mskCT16B1_PWM6MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 12)
#define mskCT16B1_PWM6MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 12)

																			//[15:14] CT16Bn PWM7 output mode.
#define mskCT16B1_PWM7MODE_1				(CT16_PWMnMODE_1 << 14)
#define mskCT16B1_PWM7MODE_2				(CT16_PWMnMODE_2 << 14)
#define mskCT16B1_PWM7MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 14)
#define mskCT16B1_PWM7MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 14)

																			//[17:16] CT16Bn PWM8 output mode.
#define mskCT16B1_PWM8MODE_1				(CT16_PWMnMODE_1 << 16)
#define mskCT16B1_PWM8MODE_2				(CT16_PWMnMODE_2 << 16)
#define mskCT16B1_PWM8MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 16)
#define mskCT16B1_PWM8MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 16)

																			//[19:18] CT16Bn PWM9 output mode.
#define mskCT16B1_PWM9MODE_1				(CT16_PWMnMODE_1 << 18)
#define mskCT16B1_PWM9MODE_2				(CT16_PWMnMODE_2 << 18)
#define mskCT16B1_PWM9MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 18)
#define mskCT16B1_PWM9MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 18)

																			//[21:20] CT16Bn PWM10 output mode.
#define mskCT16B1_PWM10MODE_1				(CT16_PWMnMODE_1 << 20)
#define mskCT16B1_PWM10MODE_2				(CT16_PWMnMODE_2 << 20)
#define mskCT16B1_PWM10MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 20)
#define mskCT16B1_PWM10MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 20)

																			//[23:22] CT16Bn PWM11 output mode.
#define mskCT16B1_PWM11MODE_1				(CT16_PWMnMODE_1 << 22)
#define mskCT16B1_PWM11MODE_2				(CT16_PWMnMODE_2 << 22)
#define mskCT16B1_PWM11MODE_FORCE_0	(CT16_PWMnMODE_FORCE_0 << 22)
#define mskCT16B1_PWM11MODE_FORCE_1	(CT16_PWMnMODE_FORCE_1 << 22)

/* CT16Bn PWM Enable register <CT16Bn_PWMCTRL> (0xA0) (CT16B0 only) */
																			//[0:0] CT16Bn PWM0 enable.
#define mskCT16B1_PWM0EN_EN					(CT16_PWMnEN_EN << 0)
#define mskCT16B1_PWM0EN_EM0				(CT16_PWMnEN_EMn << 0)

																			//[1:1] CT16Bn PWM1 enable.
#define mskCT16B1_PWM1EN_EN					(CT16_PWMnEN_EN << 1)
#define mskCT16B1_PWM1EN_EM0				(CT16_PWMnEN_EMn << 1)

																			//[2:2] CT16Bn PWM2 enable.
#define mskCT16B1_PWM2EN_EN					(CT16_PWMnEN_EN << 2)
#define mskCT16B1_PWM2EN_EM0				(CT16_PWMnEN_EMn << 2)

																			//[3:3] CT16Bn PWM3 enable.
#define mskCT16B1_PWM3EN_EN					(CT16_PWMnEN_EN << 3)
#define mskCT16B1_PWM3EN_EM0				(CT16_PWMnEN_EMn << 3)

																			//[4:4] CT16Bn PWM4 enable.
#define mskCT16B1_PWM4EN_EN					(CT16_PWMnEN_EN << 4)
#define mskCT16B1_PWM4EN_EM0				(CT16_PWMnEN_EMn << 4)

																			//[5:5] CT16Bn PWM5 enable.
#define mskCT16B1_PWM5EN_EN					(CT16_PWMnEN_EN << 5)
#define mskCT16B1_PWM5EN_EM0				(CT16_PWMnEN_EMn << 5)

																			//[6:6] CT16Bn PWM6 enable.
#define mskCT16B1_PWM6EN_EN					(CT16_PWMnEN_EN << 6)
#define mskCT16B1_PWM6EN_EM0				(CT16_PWMnEN_EMn << 6)

																			//[7:7] CT16Bn PWM7 enable.
#define mskCT16B1_PWM7EN_EN					(CT16_PWMnEN_EN << 7)
#define mskCT16B1_PWM7EN_EM0				(CT16_PWMnEN_EMn << 7)

																			//[8:8] CT16Bn PWM8 enable.
#define mskCT16B1_PWM8EN_EN					(CT16_PWMnEN_EN << 8)
#define mskCT16B1_PWM8EN_EM0				(CT16_PWMnEN_EMn << 8)

																			//[9:9] CT16Bn PWM9 enable.
#define mskCT16B1_PWM9EN_EN					(CT16_PWMnEN_EN << 9)
#define mskCT16B1_PWM9EN_EM0				(CT16_PWMnEN_EMn << 9)

																			//[10:10] CT16Bn PWM10 enable.
#define mskCT16B1_PWM10EN_EN				(CT16_PWMnEN_EN << 10)
#define mskCT16B1_PWM10EN_EM0				(CT16_PWMnEN_EMn << 10)

																			//[11:11] CT16Bn PWM11 enable.
#define mskCT16B1_PWM11EN_EN				(CT16_PWMnEN_EN << 11)
#define mskCT16B1_PWM11EN_EM0				(CT16_PWMnEN_EMn << 11)

/* CT16Bn PWM IO Enable register <CT16Bn_PWMCTRL> (0xA4) */
																			//[0:0] CT16Bn PWM0 IO selection.
#define mskCT16B1_PWM0IOEN_EN				(CT16_PWMnIOEN_EN << 0)
#define mskCT16B1_PWM0IOEN_DIS			(CT16_PWMnIOEN_DIS << 0)

																			//[1:1] CT16Bn PWM1 IO selection.
#define mskCT16B1_PWM1IOEN_EN				(CT16_PWMnIOEN_EN << 1)
#define mskCT16B1_PWM1IOEN_DIS			(CT16_PWMnIOEN_DIS << 1)

																			//[2:2] CT16Bn PWM2 IO selection.
#define mskCT16B1_PWM2IOEN_EN				(CT16_PWMnIOEN_EN << 2)
#define mskCT16B1_PWM2IOEN_DIS			(CT16_PWMnIOEN_DIS << 2)

																			//[3:3] CT16Bn PWM3 IO selection.
#define mskCT16B1_PWM3IOEN_EN				(CT16_PWMnIOEN_EN << 3)
#define mskCT16B1_PWM3IOEN_DIS			(CT16_PWMnIOEN_DIS << 3)

																			//[4:4] CT16Bn PWM4 IO selection.
#define mskCT16B1_PWM4IOEN_EN				(CT16_PWMnIOEN_EN << 4)
#define mskCT16B1_PWM4IOEN_DIS			(CT16_PWMnIOEN_DIS << 4)

																			//[5:5] CT16Bn PWM5 IO selection.
#define mskCT16B1_PWM5IOEN_EN				(CT16_PWMnIOEN_EN << 5)
#define mskCT16B1_PWM5IOEN_DIS			(CT16_PWMnIOEN_DIS << 5)

																			//[6:6] CT16Bn PWM6 IO selection.
#define mskCT16B1_PWM6IOEN_EN				(CT16_PWMnIOEN_EN << 6)
#define mskCT16B1_PWM6IOEN_DIS			(CT16_PWMnIOEN_DIS << 6)

																			//[7:7] CT16Bn PWM7 IO selection.
#define mskCT16B1_PWM7IOEN_EN				(CT16_PWMnIOEN_EN << 7)
#define mskCT16B1_PWM7IOEN_DIS			(CT16_PWMnIOEN_DIS << 7)

																			//[8:8] CT16Bn PWM8 IO selection.
#define mskCT16B1_PWM8IOEN_EN				(CT16_PWMnIOEN_EN << 8)
#define mskCT16B1_PWM8IOEN_DIS			(CT16_PWMnIOEN_DIS << 8)

																			//[9:9] CT16Bn PWM9 IO selection.
#define mskCT16B1_PWM9IOEN_EN				(CT16_PWMnIOEN_EN << 9)
#define mskCT16B1_PWM9IOEN_DIS			(CT16_PWMnIOEN_DIS << 9)

																			//[10:10] CT16Bn PWM10 IO selection.
#define mskCT16B1_PWM10IOEN_EN			(CT16_PWMnIOEN_EN << 10)
#define mskCT16B1_PWM10IOEN_DIS			(CT16_PWMnIOEN_DIS << 10)

																			//[11:11] CT16Bn PWM11 IO selection.
#define mskCT16B1_PWM11IOEN_EN			(CT16_PWMnIOEN_EN << 11)
#define mskCT16B1_PWM11IOEN_DIS			(CT16_PWMnIOEN_DIS << 11)

/* CT16Bn Timer Raw Interrupt Status register <CT16Bn_RIS> (0xA8) */
/* CT16Bn Timer Interrupt Clear register <CT16Bn_IC> (0xAC) */
/* The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS*/
#define mskCT16_MR0IF								(0x1 << 0) //[0:0] Interrupt flag for match channel 0
#define mskCT16_MR0IC								mskCT16_MR0IF 
#define mskCT16_MR1IF								(0x1 << 1) //[1:1] Interrupt flag for match channel 1
#define mskCT16_MR1IC								mskCT16_MR1IF 
#define mskCT16_MR2IF								(0x1 << 2) //[2:2] Interrupt flag for match channel 2
#define mskCT16_MR2IC								mskCT16_MR2IF 
#define mskCT16_MR3IF								(0x1 << 3) //[3:3] Interrupt flag for match channel 3
#define mskCT16_MR3IC								mskCT16_MR3IF 
#define mskCT16_CAP0IF							(0x1 << 4) //[4:4] Interrupt flag for capture channel 0
#define mskCT16_CAP0IC							mskCT16_CAP0IF 
#define mskCT16_MR9IF								(0x1 << 5) //[5:5] Interrupt flag for match channel 9
#define mskCT16_MR9IC								mskCT16_MR9IF

/* CT16Bn Timer Raw Interrupt Status register <CT16Bn_RIS> (0xA8) (CT16B1 only) */
/* CT16Bn Timer Interrupt Clear register <CT16Bn_IC> (0xAC) (CT16B1 only) */
/* The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS*/
#define mskCT16B1_MR0IF							(0x1 << 0) //[0:0] Interrupt flag for match channel 0
#define mskCT16B1_MR0IC							mskCT16B1_MR0IF 
#define mskCT16B1_MR1IF							(0x1 << 1) //[1:1] Interrupt flag for match channel 1
#define mskCT16B1_MR1IC							mskCT16B1_MR1IF 
#define mskCT16B1_MR2IF							(0x1 << 2) //[2:2] Interrupt flag for match channel 2
#define mskCT16B1_MR2IC							mskCT16B1_MR2IF 
#define mskCT16B1_MR3IF							(0x1 << 3) //[3:3] Interrupt flag for match channel 3
#define mskCT16B1_MR3IC							mskCT16B1_MR3IF 
#define mskCT16B1_MR4IF							(0x1 << 4) //[4:4] Interrupt flag for match channel 4
#define mskCT16B1_MR4IC							mskCT16B1_MR4IF 
#define mskCT16B1_MR5IF							(0x1 << 5) //[5:5] Interrupt flag for match channel 5
#define mskCT16B1_MR5IC							mskCT16B1_MR5IF 
#define mskCT16B1_MR6IF							(0x1 << 6) //[6:6] Interrupt flag for match channel 6
#define mskCT16B1_MR6IC							mskCT16B1_MR6IF 
#define mskCT16B1_MR7IF							(0x1 << 7) //[7:7] Interrupt flag for match channel 7
#define mskCT16B1_MR7IC							mskCT16B1_MR7IF 
#define mskCT16B1_MR8IF							(0x1 << 8) //[8:8] Interrupt flag for match channel 8
#define mskCT16B1_MR8IC							mskCT16B1_MR8IF 
#define mskCT16B1_MR9IF							(0x1 << 9) //[9:9] Interrupt flag for match channel 9
#define mskCT16B1_MR9IC							mskCT16B1_MR9IF 
#define mskCT16B1_MR10IF						(0x1 << 10) //[10:10] Interrupt flag for match channel 10
#define mskCT16B1_MR10IC						mskCT16B1_MR10IF 
#define mskCT16B1_MR11IF						(0x1 << 11) //[11:11] Interrupt flag for match channel 11
#define mskCT16B1_MR11IC						mskCT16B1_MR11IF 
#define mskCT16B1_MR12IF						(0x1 << 12) //[12:12] Interrupt flag for match channel 12
#define mskCT16B1_MR12IC						mskCT16B1_MR12IF 
#define mskCT16B1_CAP0IF						(0x1 << 13) //[13:13] Interrupt flag for capture channel 0
#define mskCT16B1_CAP0IC						mskCT16B1_CAP0IF 

/* CT16Bn PWMmN IO Control register <CT16Bn_PWMmNIOCTRL> (0xB0) */
#define	CT16_PWMnN_GPIO							0	// PWMnN pin acts as GPIO
#define	CT16_PWMnN_MODE1						1 // PWMnN pin outputs the inverse signal with dead-band of PWMn, but same High signal during dead-band period.
#define	CT16_PWMnN_MODE2						2 // PWMnN pin outputs the inverse signal with dead-band of PWMn, but same Low signal during dead-band period.
#define	CT16_PWMnN_MODE3						3 // PWMnN pin outputs the same signal with dead-band of PWMn.

																			//[1:0] CT16Bn PWM0N IO selection.
#define mskCT16_PWM0N_GPIO					(CT16_PWMnN_GPIO << 0)
#define mskCT16_PWM0N_MODE1					(CT16_PWMnN_MODE1 << 0)
#define mskCT16_PWM0N_MODE2					(CT16_PWMnN_MODE2 << 0)
#define mskCT16_PWM0N_MODE3					(CT16_PWMnN_MODE3 << 0)

																			//[3:2] CT16Bn PWM1N IO selection.
#define mskCT16_PWM1N_GPIO					(CT16_PWMnN_GPIO << 2)
#define mskCT16_PWM1N_MODE1					(CT16_PWMnN_MODE1 << 2)
#define mskCT16_PWM1N_MODE2					(CT16_PWMnN_MODE2 << 2)
#define mskCT16_PWM1N_MODE3					(CT16_PWMnN_MODE3 << 2)

																			//[5:4] CT16Bn PWM2N IO selection.
#define mskCT16_PWM2N_GPIO					(CT16_PWMnN_GPIO << 4)
#define mskCT16_PWM2N_MODE1					(CT16_PWMnN_MODE1 << 4)
#define mskCT16_PWM2N_MODE2					(CT16_PWMnN_MODE2 << 4)
#define mskCT16_PWM2N_MODE3					(CT16_PWMnN_MODE3 << 4)

																			//[7:6] CT16Bn PWM3N IO selection.
#define mskCT16_PWM3N_GPIO					(CT16_PWMnN_GPIO << 6)
#define mskCT16_PWM3N_MODE1					(CT16_PWMnN_MODE1 << 6)
#define mskCT16_PWM3N_MODE2					(CT16_PWMnN_MODE2 << 6)
#define mskCT16_PWM3N_MODE3					(CT16_PWMnN_MODE3 << 6)

#define	PWM_KEY											(0x5A << 24)

/*_____ M A C R O S ________________________________________________________*/

/*_____ D E C L A R A T I O N S ____________________________________________*/

#endif	/*__SN32F290_CT16_H*/

